In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, the synchronous memory device latches internal data words from an internal data bus into latches in synchronism with the external clock signal, and data is driven from these latches to an external data bus and an external circuit, such as a memory controller, must latch these data words at the proper times to successfully capture each data word. To latch the internal data words, an internal clock signal is developed in response to the external clock signal, and is typically applied to storage circuits such as latches contained in the memory device to thereby clock the internal data words into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the internal data words. In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay or advance, causing the internal clock signal to be phase shifted relative to the external clock signal. To increase the rate at which commands can be applied to the memory device and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different clock synchronization circuits have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs). Note that as used herein, the term synchronized includes signals that are coincident and signals that have a desired phase shift relative to one another. Some clock synchronization circuits provide a fixed phase shift of the internal clock signal relative to the external signal and thereafter adjust this phase shift as a function of temperature and/or voltage. Other clock synchronization circuits have fuses that may be selectively programmed to establish a desired phase shift, or include components that may be trimmed to obtain the desired phase shift.
FIG. 1 is a functional block diagram illustrating a data output circuit 100 including a conventional clock synchronization circuit 102 that generates a synchronous phase shifted clock signal CLKDEL in response to an external clock signal CLK, and applies the CLKDEL signal to latch read data signals RD1–RDN into a plurality of data drivers 104A–N, as will now be explained in more detail. The clock synchronization circuit 102 may be any of the conventional circuits previously described, such as a DLL. The data output circuit 100 corresponds to circuitry in a typical synchronous memory device that clocks read data out of the memory device in synchronism with the CLK signal. The data drivers 104A–N receive the RD1–RDN signals, respectively, and each data driver latches the received RD1–RDN signal in response to being clocked by the CLKDEL signal and outputs the latched RD1–RDN signal as a corresponding data signal DQ1–DQN. The DQ1–DQN signals collectively form a data bus DQ of the memory device containing the data output circuit 100. In operation, the clock synchronization circuit 102 applies the CLKDEL signal to clock the RD1–RDN signals out of the data drivers 104A–N as the DQ1–DQN signals. The CLKDEL signal has a time delay TD relative to the CLK signal that causes the DQ1–DQN signals to be output from the data drivers 104A–N in synchronism with the CLK signal, as will be appreciated by those skilled in the art. Instead of viewing the CLKDEL signal as being delayed relative to the CLK signal, the CLKDEL signal may be viewed as having a phase shift relative to the CLK signal, and depending on the specific type of clock synchronization circuit 102 the CLKDEL signal may be delayed or advanced relative to the CLK signal, as will also be appreciated by those skilled in the art. The term phase shift includes both advanced and delayed CLKDEL signals relative to the CLK signal.
In a typical synchronous memory device containing the data output circuit 100, a timing parameter known as an access time TAC is specified for the memory device. The access time TAC defines a timing window around the transition of the CLK signal that defines when the transitions of the DQ1–DQN signals must occur in order to allow a memory controller to successfully capture the DQ1–DQN signals in response to the CLK signal. Typically, the access time TAC is defined as two separate parameters, a minimum access time TAC (MIN) and a maximum access time TAC, that define the maximum time before and after, respectively, the transition of the CLK signal that the transition of the DQ1–DQN signals must occur. Thus, the clock synchronization circuit 102 must operate to generate the CLKDEL signal having the time delay TD that causes the DQ1–DQN signals to satisfy the specified access time TAC parameters of the memory device containing the data output circuit 100. As long as the transitions of the DQ1–DQN signals occur within the specified access times, the DQ1–DQN signals are synchronized with the CLK signal.
In modern synchronous memory devices, the frequency of the CLK signal is steadily increasing to increase the rate at which data may be transferred to and from the memory device. As the frequency of the CLK signal increases, the access time TAC decreases, as will be appreciated by those skilled in the art. As a result, the CLKDEL signal must have the proper time delay TD relative to the CLK signal in order to clock the DQ1–DQN signals out of the data drivers 104A–N within the reduced timing window defined by the reduced access time TAC. While conventional clock synchronization circuits 102 such as DLLs can generate the CLKDEL signal having the required time delay TD, any change in the operating characteristics of the data drivers 104A–N may result in an undesirable shift in the timing of the DQ1–DQN signals relative to the CLK signal, as will be understood by those skilled in the art. For example, where the clock synchronization circuit 102 is a DLL, the DLL includes a model delay component that models a delay D introduced by the data drivers 104A–N. The delay D of each data driver 104A–N is the delay between the DQ1–DQN signal and the CLKDEL signal, and corresponds to the delay between when the data driver is clocked by the CLKDEL signal and when the clocked RD1–RDN signal is output as the corresponding DQ1–DQN signal. Differences in the actual delay D of the data drivers 104A–N and the delay corresponding to the model delay may result in the DQ1–DQN signals being output outside of the permitted window defined by the specified access time TAC.
In modern synchronous memory devices, a width N of the data bus DQ, which is determined by the number N of DQ1–DQN signals, is being increased to transfer more data to and from the memory device each cycle of the CLK signal. This increase in the width N of the data bus DQ may change the delay D introduced by the data drivers 104A–N and thereby undesirably shift the DQ1–DQN signals, as will now be explained in more detail. As illustrated in FIG. 1, a first supply voltage source VCCQ is coupled to the data drivers 104A–N through a power line 106 and a second supply voltage source VSSQ is coupled to the data drivers through a power line 108. As the width N of the data bus DQ increases, more data drivers 104A–N are coupled to the voltage sources VCCQ, VSSQ. The greater number of data drivers 104A–N increases the current through the power lines 106,108 when the data drivers 104A–N must drive the corresponding DQ1–DQN signal to an opposite voltage level corresponding to a complementary logic state. For example, when the current DQ1 signal from the data driver 104A is low and the RD1 signal corresponding to the next or upcoming DQ1 signal to be output from the data driver is high, the data driver draws current through the power line 106 to drive the DQ1 signal high when clocked by the CLKDEL signal.
As the width of N of the data bus DQ increases, more data drivers 104A–N may need to drive the corresponding DQ1–DQN signal from a first logic state to the complementary logic state when clocked by the CLKDEL signal. In this situation, the required current through the power lines 106,108 may be relatively high and may affect the delay D introduced by the data drivers 104A–N. For example, the maximum current that may be provided by each of the supply voltage sources VCCQ, VSSQ may be less than the maximum current required when all of the data drivers 104A–N must drive the corresponding DQ1–DQN signal from a first logic state to a complementary logic state. As a result, each data driver 104A–N receives less current than required to drive the corresponding DQ1–DQN signal to the complementary logic state according to the specified operating characteristics of the data driver. This reduced current causes the data drivers 104A–N to drive the corresponding DQ1–DQN signals to the complementary logic state more slowly and thereby increases the delay D introduced by each data driver. Similarly, physical constraints on the size of the power lines 106, 108 may result in the power lines having a resistance that causes a relatively large voltage drop to develop across the power lines when the data drivers 104A–N demand the maximum current due to all the data drivers driving the corresponding DQ1–DQN signal from a first logic state to a complementary logic state. Such a voltage drop may cause the data drivers 104A–N to drive the DQ1–DQN signals to the complementary logic state more slowly and thereby increase the delay D of the data drivers.
FIG. 2 illustrates the effect of the increased delay D of the data drivers 104A–N on the operation of the data output circuit 100. At a time T0, the CLKDEL signal goes high and the CLKsignal goes high later at a time T1. The CLKDEL signal goes high at time T0 before the CLK signal at time T1 to compensate for the delays D of the data drivers 104A–N, as will be appreciated by those skilled in the art. A first signal timing diagram illustrates a situation where only one of the DQ1–DQN signals transitions from a first logic state to a complementary logic state in response to the CLKDEL signal. In this situation, the DQ1–DQN signals transition at a time T2 which occurs a delay D1 after the transition of the CLKDEL signal at the time T1, where the delay D1 corresponds to the delays of the data drivers 104A–N in this situation. Note that this transition of the DQ1–DQN signals at the time T2 occurs within a specified access time TAC defined between the time T1 and a time T3.
A second signal timing diagram illustrates a situation where half the DQ1–DQN signals transitions from a first logic state to a complementary logic state in response to the CLKDEL signal. In this situation, the DQ1–DQN signals transition at a time T4 which occurs a delay D2 after the transition of the CLKDEL signal at the time T0, where the delay D2 corresponds to the delays of the data drivers 104A–N in this situation. Note that this transition of the DQ1–DQN at the time T4 also occurs within the access time TAC defined between the times T0–T3 as required. A third signal timing diagram illustrates a situation where all the DQ1–DQN signals transition from a first logic state to a complementary logic state in response to the CLKDEL signal. In this situation, the DQ1–DQN signals transition at a time T5 which occurs a delay D3 after the transition of the CLKDEL signal at the time T0, where the delay D3 corresponds to the delays of the data drivers 104A–N in this situation. Note that this transition of the DQ1–DQN at the time T5 occurs outside the access time TAC defined between the times T0–T3 and thus does not satisfy the specified access time parameter of the memory device containing the circuit 100, which is impermissible and may result in invalid data being captured by a memory controller coupled to the memory device. Thus, in the conventional data output circuit 100, when the width N of the data bus DQ becomes large and all DQ1–DQN signals on this data bus transition from a first logic state to a complementary logic state, the transition of the DQ1–DQN signals may not occur within the specified access time TAC.
There is a need for a data output circuit that provides data signals in synchronism with an applied external clock signal in wide data bus synchronous memory devices.